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preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 1 dual regulators - synchronous buck pwm dc-dc and linear controller general description the rt9205/a is a dual-output power controllers designed for high performance graphics cards and personal computers. the ic integrates a synchronous buck controller , a linear controller and protection functions into a small 14-pin package. the rt9205/a uses an internal compensated voltage mode pwm control for simplying design. an internal 0.8v reference allows the output voltage to be precisely regulated to meet low output voltage requirement. a fixed 300khz oscillation frequency reduces the component size for saving board area. the rt9205/a also features over voltage protection (ovp) and under voltage lock-out (uvlo). applications pc motherboard cable modems, set-top-box, and xdsl modems dsp and core communications processor supplies memory power supplies personal computer peripherals industrial power supplies 5v input dc-dc regulators low voltage distributed power supplies graphic cards features operates at 5v 0.8v internal reference drives two n-channel mosfet voltage mode pwm control fast transient response fixed 300khz oscillator frequency dynamic 0~100% duty cycle internal pwm loop compensation internal soft-start adaptive non-overlapping gate driver over-voltage protection uses lower mosfet pin configurations part number pin configurations rt9205/acs (plastic sop-14) top view ordering information rt9205/a lgate pgnd gnd vcc 1 2 3 4 14 13 12 11 ugate boo t nc nc drv fbl nc 5 6 7 10 9 8 nc fb nc operating temperature range c : commercial standard package type s : sop-14 uvp : hiccup mode uvp : latch mode
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 2 typical application circuit fig.1 rt9205/a powered form 5v fb fbl drv vcc rt9205/a boot ugate gnd lgate 4 5 6 9 1 3 14 13 + + s1 g1 2 1 s2 g2 4 3 d1 d1 7 8 d2 d2 5 6 + + + 5v q1 2sd180 2 ce1 100 f v out2 3.4v v out2 = 0.8*(1+r1/r2) c6 1 f ce5 470 f r1 390 c4 10n f r2 120 c1 1 f d1 1n5819 c3 0.1 f pha se r4 200 r4 < 1k r2 < 1k 0.8v r3 200 c7 10n f v out1 = 0.8v*(1+r3/r4) pull fb tra ce out after c out l1 1 h c2 1 f ce2 680 f l2 5 h be careful during la you t pha se 5v 5v c5 1 f ce3 680 f lesr ce4 680 f lesr v out1 1.6v pgnd 2 phkd6n02lt
preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 3 fig.2 rt9205/a powered from 12v dr v fbl vcc boot ugat e gnd lgate rt9205/a 9 13 14 3 1 4 5 6 fb r1 430 r2 200 + + c6 1uf ce7 470uf v out2 2.5v v out2 = 0.8 v*(1+ r1 /r2) r2<1k c4 10nf 0. 8v ce 1 100uf 3.3v q1 2sd5706 ce3 1000uf + ce2 1000uf be careful during layout l2 5uh c5 1uf ce4 ce5 v ou t1 1.7v r3 200 r4 200 c7 10nf v out1 = 0 .8v *(1 +r 3 /r4 ) phase pull fb trace out after c ou t su gge st u se tr ansisto r c1 1uf r5 2.2 c2 0.1uf r6 10 5v 12v + c3 1uf 5v l1 1uh + + + 1000uf lesr ce4 1000uf lesr ce5 1000uf lesr phb66 nq 03l t p hb 108 nq 03l t pgnd
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 4 layout placement layout notes 1. put c1 & c2 to be near the mu drain and ml source nodes. 2. put rt9205/a to be near the c out 3. put c boot as close as to boot pin 4. put c vcc as close as to vcc pin function block diagram + gnd boot rt9205/a vcc c vcc 1 f c out 100 0 f + gs mu d gs ml d c boot 0.1 f l 5 h c1 1 f c2 470 f gnd return 6.0v regulator control logic po w er on reset sof t start 0.8v ref er enc e 300khz oscillator _ + _ amp + _ uvp + _ ovp vcc fb gnd boot uga t e lgate vcc error 0.8v 1v + _ uvp _ ldo + + + pwm + ss drv fbl 0.5 v v cc 6.0v regulator 6.0v regulator control logic control logic po w er on reset po w er on reset sof t start sof t start 0.8v ref er enc e 0.8v ref er enc e 300khz oscillator 300khz oscillator _ + _ amp + _ uvp + _ ovp vcc fb gnd boot uga t e lgate vcc error 0.8v 1v + _ uvp _ ldo + + + pwm + ss drv fbl 0.5 v v cc
preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 5 absolute maximum ratings supply voltage vcc 7 v boot & ugate to gnd 19v input, output or i/o voltage gnd ? 0.3v ~ 7v package thermal resistance sop-14, ja 160 c/w ambient temperature range 0 c ~ +70 c junction temperature range -40 c ~ +125 c storage temperature range ? 65 c ~ +150 c lead temperature (soldering, 10 sec.) 260 c caution: stresses beyond the ratings specified in ?absolute maxi mum ratings? may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions abov e those indicated in the operational sections of this s pecification is not implied. electrical characteristics (v cc = 5v, t a = 25 c, unless otherwise specified.) parameter symbol test conditions min typ max units vcc supply current nominal supply current i cc ugate, lgate open -- 3 -- ma vcc regulated voltage i cc v boot = 12v 5 6 7 v power-on reset rising vcc threshold 3.8 4.1 4.4 v vcc threshold hysteresis -- 0.5 -- v reference reference voltage v fb both pwm and linear regulator 0.784 0.8 0.816 v oscillator free running frequency 250 300 350 khz ramp amplitude ? v osc -- 1.75 -- v p-p pwm error amplifier dc gain 32 35 38 db pwm controller gate driver upper drive source r ugate boot= 12v boot-v ugate = 1v -- 7.5 11 ? upper drive sink r ugate v ugate = 1v -- 5 8 ? lower drive source r lgate vcc - v lgate = 1v, -- 3.5 6 ? lower drive sink r lgate v lgate = 1v -- 2 5 ? linear regulator drv driver source v drv = 2v 100 -- -- ma protection fb over-voltage trip fb rising 0.9 1 -- v fb & fbl under-voltage trip fb & fbl falling -- 0.5 0.65 v soft-start interval -- 2.5 -- ms
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 6 functional pin description lgate (pin 1) connect the lgate pin to the gate of lower mosfet. this pin provides the gate drive for the lower mosfet. pgnd/gnd (pin 2, 3) signal and power ground for the ic. all voltage levels are measured with respect to this pin. vcc (pin 4) this is the main bias supply for the rt9205/a. this pin also provides the gate bias charge for the gate of lower mosfet. the voltage at this pin is monitored for ensuring a proper power-on reset (por). this pin is also the out of an internal 6.0v regulator that powered from the boot pin when the boot pin is directly powered from atx 12v. drv (pin 5) this pin is the output of a linear controller. it should be connected to the base of an external bypass npn transistor or the gate of a n-mosfet to form a linear low dropout regulator. fbl (pin 6) this pin is connected to the output resistor-divider of an external power transistor or a n-mosfet based low dropout regulator for regulating and monitoring the output voltage. this pin is also connected to the protection monitor and the invertering input of error amplifier of internal linear regulator inside the ic. fb (pin 9) this pin is connected to the pwm converter?s output ? divider for regulating and monitoring the output voltage of buck converter. this pin also connects to the protection monitor and the inverting input of internal pwm error amplifier inside the ic. boot (pin 13) this pin provides ground referenced bias voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage that is suitable for driving a logic-level n-channel mosfet when operating at a single 5v power supply. this pin also could be powered from atx 12v, in this situation, an internal 6.0v regulator will supply to vcc pin fo r generating bias required inside the ic. ugate (pin 14) connect the ugate pin to the gate of upper mosfet. this pin provides the gate drive for the upper mosfet.
preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 7 typical operating charateristics time ugate lgate v cc = 5v dead time dead time time lgate v cc = 5v ugate load transient time ugate v cc = 5v v out = 2.2v c out = 3000 f v out load transient time ugate v cc = 5v v out = 2.2v c out = 3000 f v out power on time v cc v cc = 5v v out1 = 2.5v v out2 = 1.8v v out1 v out2 power off time v cc v cc = 5v v out1 = 2.5v v out2 = 1.8v v out1 v out2
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 8 bootstrap wave form time lgate v cc = 5v; v out = 2.2v ugate phase reference vs. temperature 0.796 0.797 0.798 0.799 0.800 0.801 0.802 0.803 -50 0 50 100 150 temperature ( c) reference (v) i ocset vs. temperature 20 25 30 35 40 45 50 55 -40 -10 20 50 80 110 140 temperature ( c) i ocset ( a) por (rising/falling) vs. temperature 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 -50 0 50 100 150 temperature ( c) por (v) falling rising short hiccup time (2ms/div) v out v cc = 5v v out = 2.2v ugate RT9205A short hiccu p ( latch mode ) time (2ms/div) v out v cc = 5v v out = 2.2v ugate rt9205
preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 9 oscillator frequency vs. temperature 270 275 280 285 290 295 300 305 310 315 -50 0 50 100 150 temperature ( c) frequency (khz)
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 10 functional description the rt9205/a operates at either single 5v power supply with a bootstrap ugate driver or a 5v/12v dual-power supply form the atx smps. the dual- power supply is recommended for high current applications, the rt9205/a can deliver higher gate driving current while operating with atx smps based on a dual-power supply. the bootstrap operation in a single power supply system, the ugate driver of rt9205/a is powered by an exte rnal bootstrap circuit, as shown in the fig.3. the boot capacitor, c boot , generates a floating reference at the phase pin. typically a 0.1 f c boot is enough for most of mosfets used with the rt9205/a. the voltage drop between boot and phase is refreshed to a voltage of vcc ? diode drop (v d ) while the lower mosfet turning on. fig.3 single 5v power supply operation dual power operation the rt9205/a was designed to supply a regulated 6.0v at vcc pin automatically when boot pin is powered by a 12v. in a system with atx 5v/12v power supply, the rt9205/a is ideal for higher current applications due to the higher gate driving capability, v ugate = 12v and v lgate = 6.0v. a rc (10 ? /1 f) filter is also recommended at boot pin to prevent the ringing induced from fast power-on, as shown in fig.4. fig.4 dual power supply operation power on reset the power-on reset (por) monitors the supply voltage (normal +5v) at the vcc pin and the input voltage at the ocset pin. the vcc por level is set to 4.1v with 0.5v hysteresis and the normal level at ocset pin is set to 1.5v (see over-current protection). the por function initiates soft-start operation after all supply voltages exceed their por thresholds. soft start a built-in soft-start is used to prevent surge current from power supply input during powering on. the soft-start voltage is controlled by an internal digital counter. it slows down and clamps the ramping of reference voltage at the input of error amplifier and the pulse-width of the output driver. the typical soft- start duration is 2.5ms. under voltage and over voltage protection the voltage presents at fb pin is monitored and protected against oc (over current), uv (under voltage), and ov (over voltage). the uv threshold is 0.56v and ov-threshold is 1.0v. both uv and ov detection are with 30 s delay after triggered. when oc or uv trigged, a hiccup re-start sequence will be initialized, as shown in fig.5. for rt9205, only 3 times of trigger are allowed before latching off. but for RT9205A, uvp will be kept in hiccup mode. hiccup is disabled during soft-start interval. + boot ugate phase lgate rt9205/a vcc d1 0.1 f 5v r1 c2 1 f vcc + 5v vcc lgate ugate boot r c2 1uf rt9205/a 1uf 6.0v regulation 10 c 12v vcc
preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 11 fig. 5 applications information inductor selection the rt9205/a was designed for v in = 5v, step-down application mainly. fig.6 shows the typical topology and waveforms of step-down converter. the ripple current of inductor can be calculated as follows: il ripple = (5v - v out )/l t on because operation frequency is fixed at 300khz, t on = 3.33 v out /5v the v out ripple is v out ripple = il ripple esr esr is the equivalent series resistor of output capacitor table 1 shows the ripple voltage of v out at vin = 5v table 1 fig. 6 v out 3.3v 2.5v 1.5v inductor 2 h 5 h 2 h 5 h 2 h 5 h 1000 f (esr=53m ? ) 100mv 40mv 110mv 44mv 93mv 37mv 1500 f (esr=33m ? ) 62mv 25mv 68mv 28mv 58mv 23mv 3000 f (esr=21m ? ) 40mv 16mv 43mv 18mv 37mv 15mv *refer to sanyo low esr series (ce, dx, px?) the suggested l and c are as follows: 2 h with 1500 f c out 5 h with 1000 f c out t on t off t s v l v i - v o - v o i l = i o i l q i l i q i q i d i d c.c.m. v l r v o l dc q v i 0a 0v 2v 4v internal ss inductor current t0t1 t2 t3 time count = 1 count = 2 count = 3 overload applied
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 12 input / output capacitor high frequency/long life decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance to the pcb trace, as it could eliminate the performance from utilizi ng these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. the output capacitors are necessary for filtering output and stabilizing the close loop (see the pwm loop stability). for power ing advanced high-speed processors, it is required to meet fast load transient requirement. also high esr usually induces ripple that may trigger uv or ov protections. so high frequency capacitors with low esr/esl capacitors are recommended here. linear regulator driver the linear controller of rt9205/a was designed to drive an external bipolar npn transistor or a n- channel mosfet. for a n-channel mosfet, normally drv need to provide minimum v out2 +vt+gate-drive voltage to keep v out2 as the set voltage. when driving mosfet operating at a 5v power supply, the gate-drive will be limited at 5v. at this situation, as shown in fig.7, a mosfet with low vt threshold (vt = 1v) and set vout2 below 2.5v are suggested. in v boot = 12v operation condition, as fig.8 shown, vcc is regulated higher than 6v, which providing higher gate-drive capability for driving the mosfet, v out2 can be set as v out2 3.3v. fig. 7 fig. 8 pwm loop stability the rt9205/a is a voltage mode buck controller designed for 5v step-down applications. the gain of error amplifier is fixed at 35db for simplifying design. the output amplitude of ramp oscillator is 1.6v, the loop gain and loop pole/zero are calculated as follows: dc loop gain g a = 35db lc filter pole p o = error amp pole p a = 300khz esr zero z o = the rt9205/a bode plot is as shown in fig.9. it is stable in most of application conditions. loop gain v ou t = 1.5v v ou t = 2.5v v ou t = 3.3v z o = 3.2khz p o = 2.9khz l=2 h c out = 1500 f(33m ? ) v ou t = 3.3v 40 30 20 10 1m 100k 10k 1k 100 fig. 9 75 . 1 5 vout 8 . 0 + fbl vcc rt9205/a v out2 3.3v r3 boot drv v bo ot = 12v r4 r4 < 1k 6v max. 6v suggest low v t mosfet + fbl vcc rt9205/a v out2 2.5v r3 boot drv vcc = 5v r4 r4 < 1k max. 5v suggest low v t mosfet lc 2 1 c esr 2 1
preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 13 reference voltage because rt9205/a uses a low 35db gain error amplifier, as shown in fig.10. the voltage regulation is dependent on v in and v out settings. the fb reference voltage of 0.8v were trimmed at v in = 5v and v out = 2.5v. in a fixed v in = 5v application, the fb reference voltage vs. v out voltage can be calculated as fig.11. fig. 10 fig. 11 feedback divider the reference of rt9205/a is 0.8v. the output voltage can be set using a resistor-divider as shown in fig.12. put the r1 and r2 as close as possible to fb pin. r2 value should be less than 1 k ? to avoid noise coupling issue. the c1 capacitor is a speed-up capacitor for reducing output ripple to meet with the requirement of fast transient load. typically, value between 1nf and 0.1 f is enough for c1. fig. 12 pwm layout considerations mosfets switch very fast in efficiency. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise, that resu lts in over-voltage stress on devices. careful the layout for component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. consider, as an example, the turn-off transition of the upper mosfet prior to turn-off, the upper mosfet was carrying the full load current. during turn-off, current stops flowing in the upper mosfet and is picked up by the lower mosfet or schottky diode. any inductance in the switched current path generates a large voltage spike during the switching interval. care with component selections, layout of the critical components, and use shorter and wider pcb traces that help in minimizing the magnitude of voltage spikes. there are two sets of crit ical components in a dc-dc converter using the rt9205/a. the switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. the critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. the power components and the pwm controller should be placed firstly. place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. place the output inductor and output capacitors between the + _ + _ ea + _ pwm rep 0. 8v i3 56k i2 1k fb ramp 1. 75v fb (v) duty (%) vin = 5v 80 70 60 20 30 40 50 0.82 0.78 0.80 0.81 0.79 10 90 v fb = 0.8v ? ? ? ? ? ? ? ? 100 50 duty 6.25mv v out = v fb (1+ 2 1 r r ) vin c out + v out rt9205/a fb l r1 r2 < 1k c1
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 14 mosfets and the load. also locate the pwm controller near by mosfets. a multi-layer printed circuit board is recommended. fig.13 shows the connections of the critical components in the converter. note that the capacitors cin and cout represent numerous physical capacitors. use a dedicated grounding plane and use vias to ground all critical components to this layer. apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase node, but it is not neces sary to oversize this particular island. since the phase node is subjected to very high dv/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. use the remaining printed circuit layers for small signal routing. the pcb traces between the pwm controller and the gate of mosfet and also the traces connecting source of mosfets should be sized to carry 2a peak currents. fig. 13 + + + load rt9205/a vcc gnd fb lgate ugate v out iq1 il q1 q2 iq2 5v gnd
preliminary rt9205/a ds9205/a-03 may 2003 www.richtek.com 15 package information dimensions in millimeters dimensions in inches symbol min max min max a 8.534 8.738 0.336 0.344 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.178 0.254 0.007 0.010 i 0.102 0.254 0.004 0.010 j 5.791 6.198 0.228 0.244 m 0.406 1.270 0.016 0.050 14?lead sop plastic package a b f j d c i h m
rt9205/a preliminary www.richtek.com ds9205/a-03 may 2003 16 richtek technology corp. headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corp. taipei office (marketing) 8f-1, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com

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